Rf chip testing method and system

ABSTRACT

A method and system for testing RF chips for radio specification compliance is described. The system comprises a test board ( 80 ) having a plurality of interconnected sockets ( 82   a,b,c ) for receiving chips to be tested. In testing, signals generated by transmitter circuitry ( 20 ) within a group of test chips are used to test the receiver ( 30 ) functionality of the other chips loaded in the system. Hence, for tests requiring several analogue radio signals, a plurality of chips are tested at the same time using signals generated from other chips. Additionally, the system does not require expensive dedicated RF analogue signal generating equipment.

The present invention relates to radio frequency (RF) testing methodsand further relates to a testing system suitable for practising suchmethods. The present invention has particular, but not exclusive,application in the testing of the RF functionality of integrated circuitchips and the compliance of such functionality with an intended radiostandard or specification.

Radio frequency integrated circuit (IC or ‘chip’) manufacturing requirestesting to determine whether the manufactured ICs are compliant with aradio standard (e.g. Bluetooth™, GSM™, IEEE802.15.4) and operational inother respects. Typically, a pick and place machine will place the chipdevice to be tested in a suitably constructed test board or ‘test head’of specialised automated test equipment (ATE). The ATE applies theappropriate test signals to the device under test (DUT) and passes orrejects the device. Such individual chip testing exhibits a problem inthat it is time consuming and hence adds to the overall manufacturingcost.

Another particular problem in testing the functionality of an RF chipfor compliance with a radio standard exists in that the specificationmay require the ATE to generate several specific analogue RF signals atthe same time in order to test, for example, the interferenceperformance of the receiver of the DUT. Special signal generatinghardware is therefore required, adding cost to the ATE, and thereforeexpense to the manufacturer. Furthermore, the application of suchsignals is often via long probes brought down into contact with thepin-out of the chips, requiring a specially constructed and controlledtest suite. The use of such probes results in unspecified and difficultto quantify losses reducing the accuracy of any such test.

It is therefore an object of the present invention to provide animproved method and system for RF chip testing.

According to a first aspect of the present invention there is provided amethod for testing a plurality of integrated circuit chips forcompliance with a radio standard, each chip having transmission meansand receiving means for sending and receiving RF signals, the methodcomprising:

-   -   placing the chips in close proximity to one another,    -   testing the transmission means of each chip with respect to a        known good reference chip,    -   selecting a number of the chips to form a generating group, the        remaining chips forming a receiving group, and    -   testing the receiving group using signals generated by the        generating group.

According to a further aspect of the present invention there is provideda testing system for testing a plurality of integrated circuit chips,each chip having transmission means and receiving means for sending andreceiving RF signals, the system comprising:

a computer having communication, control and data acquisition means forcommunicating with, controlling and acquiring data from testing means towhich it is connected,

the testing means comprising a plurality of chip sockets adapted tophysically accept and electronically interface with a chip placedtherein, and wherein each socket is provided with signal propagation andattenuation means for sending and receiving signals to each of the othersockets under the control of the computer,

and where in operation the computer selects a group of chips to generatetest signals which are propagated via the propagation means to areception test group of chips.

The method and system of the present invention implement applicant'sappreciation that many compliance tests in the RF field require a numberof signals to be generated, and that the RF chips being tested may beutilised in the system to generate such signals. Hence, a system isprovided in which a group of chips, having passed transmissiongeneration tests for example, are utilised to generate the signalsrequired to test the reception hardware of the other chips.

Preferably, the number of chips selected corresponds to the number ofsignals required for the particular test. For example, in aninterference test a “wanted” signal with two other “interfering signals”must be generated on certain specified channels to determine the qualityof the receiver. In such an example test, three chips are thereforerequired to be selected for the test. If one considers the situationwhere there are eight chips mounted in the system, then such aninterference test requires that three chips are selected (the generatinggroup) to provide the three signals to the remaining five chips (thereceiving test group). Following the test, three of the five chips justtested may be selected for the generation group and these then providethe signals to the previous generating group. Hence, such aninterference test only requires two “passes” to test all eight chips,and no extra signal generating hardware. This compared with eightindividual tests required in a conventional system which in additionrequires signal generating hardware to generate the three signals forthe above example test, and individual probing (which has thedisadvantage of including unknown losses due to such probing).

Advantageously, each chip's signal may be attenuated via programmableattenuators before being provided to the test group of chips. Thisallows for imbalance in transmission and reception power required for atest. For example the Bluetooth specification requires a transmissionpower of 0 dBm whilst the chips receiving hardware requires a signal ofthe order of −70 dBm, therefore the signals generated by the group ofchips require 70 dB attenuation.

In a preferred embodiment, the computer is a standard PC with a digitaldata acquisition card to interface it to the test board. The control andtest routines and analysis of data captured by the card are provided insoftware. Hence this digital test equipment is relatively inexpensiveand flexible enabling different tests for different radio specificationsto be installed or downloaded as required by the customer.

The present invention will now be described, by way of example only, andwith reference to the accompanying drawings wherein:

FIG. 1 is a block diagram of the circuitry of an RF chip being a deviceunder test (DUT);

FIG. 2 is a schematic diagram of a system for testing a chip as shown inFIG. 1;

FIG. 3 is flow diagram representing example steps of a method embodyingthe invention;

FIG. 4 is another flow diagram representing example steps of a methodembodying the invention in which intermodulation and other receivertests are performed.

It should be noted that the Figures are diagrammatic and not drawn toscale. Relative dimensions and proportions of parts of these Figureshave been shown exaggerated or reduced in size, for the sake of clarityand convenience in the drawings. The same reference signs are generallyused to refer to corresponding or similar features in modified anddifferent embodiments.

FIG. 1 shows a typical transceiver architecture for an RF chip. Thisarchitecture comprises a baseband section 10 connected with atransmission chain 20 comprising a digital to analog converter (DAC) forconverting the intended digital signal to an analogue signal, a mixingstage where the signal is mixed with the output of a frequencysynthesiser block 22 and a power amplifier for amplifying the resultingsignal. A receiving chain 30 comprises an antenna filter, a low noiseamplifier, a mixing stage, channel filtering and demodulating stage.Such a general transceiver having transmission and reception means forgenerating and transmitting/receiving signals is well known to thoseskilled in the art. In an application, for example a mobile phone orpersonal digital assistant (PDA), the transceiver is connected to anantenna for radiating or receiving radiated signals. In a testingenvironment, prior to incorporation in a final product such as a mobilephone, the transceiver (Tx) 20 and receiver (Rx) 30 blocks are connectedto relevant pins of the chip (if packaged) or a pad/probe applied to theappropriate test location on the silicon die containing the transceivercircuitry (if testing is prior to packaging).

An integrated circuit for producing for example, Bluetooth signals maydo so via such an architecture as shown in FIG. 1, together with alayered protocol. The Bluetooth protocol or specification as laid out inthe Bluetooth specification v1.1 requires the radio performance of sucha chip to meet certain test requirements. Pages 20-32 of theaforementioned specification, which are incorporated herein forreference and to which the reader is now directed, specify among othersthe following tests: output power and power control of the transmitter,sensitivity, interference performance, intermodulation characteristicand receiver signal strength indicator.

It is to be noted that several of these tests require a number ofsignals to be generated at the same time. In particular,characterisation of the receiver for interference performance involvesco-channel and adjacent channel tests which each require twotransmission signals to be generated. The characterisation and testingof the intermodulation characteristics of the receiver require threesignals to be generated—a wanted signal at a first frequency f₀ with apower level 6 dB over the reference sensitivity level, a static sinewave signal at another frequency f₁ with a power level of −39 dBm and abluetooth modulated signal at a further frequency f₂ with a power levelof −39 dBm, such that f₀−2f₁−f₂ and mod(f₂−f₁)=n*1 MHz where n can be 3,4, or 5. In general the Bit Error Rate (BER) is measured and evaluatedagainst a predetermined level (e.g. 0.1%) to provide a pass/fail forthese tests.

FIG. 2 is a diagram of a digital testing system embodying the presentinvention. The system comprises a computer in the form of a PC 40 havinga display and a digital acquisition card (DAQ) 55, a suitable examplebeing National Instruments™ PCI 7030/6030E. Testing routines, controland analysis software are provided with the computer on suitable media60, or may be downloaded over a suitable internet link (not shown). Thecomputer and DAQ are connected to a test board or “test head” 80 via aSCSI link 70 although other suitable interface links 70 may be used(IEEE1394 ‘Firewire’, and USB being common examples).

The board 80 comprises in this embodiment eight chip sockets 82 a,b,c(labelled X1,X2 to X7, and GS in the diagram) for accepting radio chipsfor testing. Each socket interfaces electronically (via techniques wellknown in the art such as tensioned pins or solderbump pads) with thechip mounted therein. Suitably designed tracks 88 with programmableattenuators 86 (A1 to A7, Ags) for interconnecting and propagatingsignals from one chip socket to another are provided. Control andinput/output (I/O) data is passed between the computer 40 and socketsvia the test head link 70. In this embodiment the socket 82 c isprovided for a “golden sample” chip. This chip has been previouslytested and characterised and is used as a reference with which tocompare the characteristics of other chips just manufactured.

FIG. 3 illustrates a flow chart example of a testing method performed bythe system of FIG. 2, and as implemented by software 60. In the methodchips are loaded into sockets 82 a,b. The golden sample socket 82 c isloaded is with a golden sample. In the basic method according to theinvention the transmission circuitry 20 of each chip is tested (step100) with respect to the golden sample. For example the power output ofeach transceiver may be measured and compared with the known goldensample power output which is within the specified Bluetoothrequirements. After testing all of the loaded chips X1-X7, the computerdetermines (step 102) whether the result was a pass or fail for eachchip and stores the result in memory. The testing then moves ontotesting the receiver chain 30 of each chip for specification compliance.

In step 104 the computer selects a first group of chips (for example thechips mounted in sockets X5, X6 and X7 as denoted by the dashed boxlabelled 82 b in FIG. 2) which will form a signal generating group forgenerating the signals which must be received by the remaining testchips 82 a in order to test the receiver circuitry 30 of those remainingchips. Under the control of the computer the receiving group of chipsare each subjected to the signals generated by the first group, therebytesting the receiver circuitry 30 of those chips in parallel (step 106).In this embodiment, the transmitted signals from X5, X6 and X7 areattenuated by the programmable attenuators A5, A6, A7 and then passeddown signal propagation tracks 88 to the receiver test group 82a of X1,X2, X3 and X4. Following step 106, the generating group becomes areceiving group to enable testing of the receiver circuitry of thosechips, and a new second generating group is selected (‘SEL 2G’ step 108)to generate the test signals. The receiving group (which acted as thefirst generating group previously) is subsequently tested in step 110and the results from the tests analysed.

Hence, RF analogue signals which are required for testing the receiverfunctionality of a radio chip are generated “on-board” by a group ofchips which themselves form part of the test. Additionally, the signalsare routed to the test chips in parallel, hence saving time andeffectively testing the receiver group of chips instantaneously.

FIG. 4 illustrates a flowchart giving a particular example of testingrequirements which are necessary for evaluating a Bluetooth™ radio chipand wherein a methodology embodying the invention is applied. In thisparticular example seven chips labelled X1 to X7 are to be tested withrespect to a golden sample for transmission characteristics (poweroutput and control) and receiver characteristics (intermodulation,co-channel, adjacent channel, sensitivity and Receiver Signal StrengthIndicator (RSSI)), wherein:

-   -   block 120—IC's X_(i) (i=1 to 7) are loaded as is the golden        sample chip, following which;    -   block 122—IC X_(i) transmits a signal s_(i) at a first frequency        f1 to the golden sample chip, and attenuator A_(i) is programmed        to reduce the power of signal s_(i), after which;    -   in block 124 the BER of the signal si as received by the golden        sample is analysed and a decision is made as to whether the        transmitter of X_(i) is either:        -   not within specification (block 126), X_(i) is characterised            as a reject and is not included in any further tests,        -   or is within specification, the result is stored and    -   in block 128, a determination is made (is i<7?) whether all        chips have been tested. If there are still chips to be tested        then i=i+1 and the program flow follows path 130 back to block        122. Once all chips have been tested (i=7) then the program flow        moves to the next required tests in block 132;    -   Block 132—Intermodulation tests are performed to determine        receiver characteristics. X1, X3 and X3 selected to provide a        wanted signal, an interfering signal and a co-channel signal        respectively. A1, A2 and A3 are programmed to limit outputs;    -   Block 134—the signals are provided by X1, X2 and X3 to the        remaining chips X4, X5, X6 and X7 and the results analysed for        each IC as to whether it:        -   Fails—block 136—IC is rejected as receiver not within            specification        -   Or passes in which case flow moves to    -   Block 138 wherein X4, X5 and X6 are selected to generate the        intermodulation test signals and A4, A5 and A6 programmable        attenuators are programmed to limit outputs, following which:    -   Block 140, the signals are provided by X4, X5 and X6 to the        remaining chips X1, X2, X3 and the results analysed for each IC        as to whether it:        -   Fails—block 142—IC is rejected as receiver not within            specification        -   Or passes in which case flow moves to    -   Block 144 wherein the remaining RF tests (co-channel, Adjacent        channel, sensitivity and RSSI calibration are performed on those        chips which have previously passed the transmitter tests (block        124) and the intermodulation receiver tests (blocks 134 and 140)        after which    -   those IC which have passed all tests are noted as being within        test specification requirements.

In the above embodiments an example testing system and methods weredescribed with reference to packaged Bluetooth™ radio chips.

In an alternative embodiment the sockets for accepting chips arereplaced with suitably designed solder pads on which singulated die maybe placed. Testing may then be executed as described previously. Hence,in this embodiment a manufacturer is able to test integrated circuitchips in the form of singulated die before packaging, thereby enablingfaster quality testing “upstream” of the packaging process.

Those skilled in the art of testing will recognise that implementing theexample testing flow charts of FIG. 3 and FIG. 4 is a matter of softwaredesign for the digital testing equipment designer. The overall softwarecontrol, interfacing and analysis aspects of the testing system may beroutinely implemented by those skilled in the art of designing andbuilding test heads and testing systems. Other well known features ofautomatic testing equipment, such as a “pick and place” machine forhandling and loading/unloading chips from the test head, and the markingof chips with ink in the event of a test failure, although not mentionedin the above embodiments, will be recognised as being compatible withthe above.

Furthermore, in the foregoing embodiments, the method and system aspectsof the present invention were described as applied to packaged chips orsingulated die IC, the IC being a Bluetooth™ compatible design. Thoseskilled in the art will recognise that the testing method and systemsaspects of the present invention can readily be applied to otherdifferent radio chips requiring confirmation of conformity with aparticular specification for which those chips are designed. Many radiochips require testing for so-called “front end linearity,” with theradio specification specifying the linearity and absolute standardsrequired. For example, radio standards such as IEEE802.15.4 (‘ZigBee’),‘GSM’, and the so called ‘3G’ telephony standards require radio chipswhich can benefit from specification testing equipment and methodsembodying the present invention.

From reading the present disclosure, other modifications will beapparent to persons skilled in the art. Such modifications may involveother features which are already known in the design, manufacture anduse of RF testing systems, test heads and component parts thereof andwhich may be used instead of or in addition to features alreadydescribed herein without departing from the spirit and scope of thepresent invention.

1. A method for testing a plurality of integrated circuit chips forcompliance with a radio standard, each chip having transmission meansand receiving means for sending and receiving RF signals, the methodcomprising: placing the chips in close proximity to one another, testing(100) the transmission means of each chip with respect to a known goodreference chip, selecting (104) a number of the chips to form agenerating group, the remaining chips forming a receiving group, andtesting the receiving group (106) using signals generated by thegenerating group.
 2. A method according to claim 1, wherein the chipsare mounted on a test board prior to testing.
 3. A method according toclaim 1 or claim 2, wherein the selection of generating and receivinggroups (104, 106) is repeated (108, 110) until all chips have beentested.
 4. A method according to claim 3, wherein the number of chipsselected to form a generating group is determined at least in part bythe testing requirements.
 5. A method according to claim 4, wherein thetesting requirements specify a test requiring at least two generatedsignals.
 6. A method according to claim 4 or claim 5, wherein thetesting requirements specify an intermodulation test requiring threegenerated signals.
 7. A testing system for testing a plurality ofintegrated circuit chips, each chip having transmission means (10, 20)and receiving means (10, 30) for sending and receiving RF signals, thesystem comprising: a computer (40) having communication, control anddata acquisition means (55) for communicating with, controlling andacquiring data from testing means to which it is connected, the testingmeans (80) comprising a plurality of chip sockets (82 a, b, c) adaptedto physically accept and electronically interface with a chip placedtherein, and wherein each socket is provided with signal propagation(88) and attenuation means (86) for sending and receiving signals toeach of the other sockets under the control of the computer (40), andwhere in operation the computer selects a group of chips (82 b) togenerate test signals which are propagated via the propagation means toa reception test group of chips (82 a).
 8. A system according to claim7, wherein the sockets are located on a test board
 80. 9. A systemaccording to claim 7 or claim 8, wherein the signals generated by theselected group are radio frequency signals.
 10. A test board (80)comprising a plurality of chip sockets (82 a, b, c) adapted tophysically accept and electronically interface with a chip placedtherein, and wherein each socket is provided with signal propagation(88) and attenuation means (86) for sending and receiving test signalsgenerated by at least one chip to each of the other sockets.
 11. Acomputer program comprising instructions for performing a methodaccording to any of claims 1 to 4 when run on a testing computer (40).12. A computer readable storage medium (60) having recorded thereon datarepresenting instructions for performing a method according to any ofclaims 1 to 6 when said data is loaded on a testing computer (40).